1. Field of the Invention
The present invention is related to data processing systems and more specifically to apparatus for tracing activity on a bus of an in-circuit emulator.
2. Prior Art
An in-circuit emulator (ICE) duplicates and imitates the behavior of a chip it emulates by using programming techniques and special machine features to permit the ICE to execute micro code written for the chip that it imitates. Microprocessors each have their own reference clocks that provide timings for internal operations. Data and memory addresses are output to an information interchange bus for each microprocessor. In some configurations, two microprocessor information interchange buses share the same address and data lines, but the buses are timing related to the two mutually asynchronous reference clocks. To test the operation of this configuration it is desirable that the contents of the two information interchange buses be multiplexed onto the same logic-analyzer trace bus in order to minimize the required number of logic analyzer trace signals.
Events appear on the information interchange bus. The arrival times of these events are not synchronized to any single clock. In fact, several agents (microprocessors), each synchronized to a different clock frequency, can output events to the bus. The frequency of operation of each microprocessor can change dynamically, such that no one microprocessor always runs faster than all of the other microprocessors.
The arrival of each event from a microprocessor is signified by a transition of a control line dedicated to that event. A separate set of control lines is dedicated to each microprocessor. Thus, microprocessor #1 generates event #1 which is signified by a transition of control line #1. Each microprocessor can generate more than one kind of event. Each different kind of event for each microprocessor is signified by a transition of a dedicated control line for that event. Thus, microprocessor #1 also generates event #2 which is signified by a transition of control line #2.
Each event is valid only for a given setup time before and a given hold time after a transition of its dedicated control line. Thus, event #1 is valid only for a given setup 1 time (setup #1) before and a given hold time (hold #1) after a transition of control line #1. Event #2 is valid only for a given setup time (setup #2) before and a given hold time (hold #2) after a transition of control line #2. All events must be transferred coherently from the asynchronous microprocessor bus to the synchronous trace bus. Arrival of events on synchronous bus trace is indicated by a level on a control line (trace bus valid).
Neither reference clock can be used to capture both information interchange buses because neither bus can be guaranteed to always operate at a frequency greater than or equal to the other bus. Also, the references clocks will not be cleanly time-multiplexed, since suitable simulation tools to prove absence of glitches during transition from the information interchange to the trace bus are not available. The trace bus clock must be asynchronous to the other two reference clocks, and that a suitable de-metastabilizing circuit must be provided that will coherently capture the contents of either microprocessor bus
It is therefore desirable to provide an in-circuit emulator in which the contents of two microprocessor interchange buses which share the same address and data lines but are time-related to two mutually asynchronous clocks, are multiplexed onto the same logic analyzer trace bus of an in-circuit emulator.